VGA
Documents
VGA BIOS- VGA Core Development Tools
- VGA Core Test Suite Sample Code
- VGA RTL Model (no longer available)
Please note that the mailing addresses listed in the above documents are no longer accurate. Also note that due to contractual obligations, the VGA RTL model referenced in some of the above documents is no longer available.
VGA BIOS (with VESA Extensions)
- Standard BIOS functions
- CGA/EGA/VGA functions 00h through 0Fh
- EGA/VGA functions 10h through 13h
- VGA functions 1Ah through 1Ch
- Compatibility standard is the IBM PS/2 Model 70
- Uses standard VGA parameter tables and font tables
- Power On Self Test (POST) with optional "sign-on" message
- VBE 3.0 compliant
- VBE 1.2 compatible functions 00h through 07h
- VBE 2.0 DAC control functions 08h and 09h
- VBE 2.0 Protected mode interface function 0Ah
- VBE 3.0 Clock control function 0Bh and enhancements to function 00h
- Display Power Management Signaling (VBE function 10h)
- Optional support for adapters that support Display Data Channel (DDC 2B) (VBE function 15h)
- OEM Extensions are available (extended modes, initialization of memory and pixel clocks, memory testing)
VGA Core Test Suite
- 92 Compatibility Tests
- Each bit of the standard VGA is tested for functionality
- Tests each VGA controller separately (CRTC, GDC, Sequencer, Attribute Controller, RAMDAC)
- BIOS independent
- Includes inter-block testing
- Includes undocumented registers
- Includes BIOS fonts and parameter tables
- Includes table of contents and index for easy look up of tests
- Compatibility standard is the IBM PS/2 Model 70
- Each test is documented and pseudo-coded for easy translation to simulation environments
- All tests use an "abstraction layer" for VGA accesses (memory and I/O) for easy porting to simulation environments
- Each test is implemented in "C" for easy modification and execution on existing hardware
- Source code included
- Training available
VGA Core Sample Implementation (C Model)
- Links into VGA Core Test Suite for verification
- Entire VGA is modeled (except states with real time dependence)
- Implemented in "C++" for easy modification and testing
- Screen output is in a standard image file format (Windows BMP's)
- Screen output generation available on any frame
- Includes golden images for all tests (in "small frame" and "standard frame" formats)
- Generates 8-bit (pre-RAMDAC) or 24-bit (post-RAMDAC) images
- Timing data (sync, blank) can be included in image data
- Complete documentation
- Includes register specification
- Includes functional block diagram
- Documents each functional block
- Bitmap Comparison Utility
- Training available